Why rustc's RISC-V targets attach combinations of ISA to instruction base sets?

By now, Rust supports the following RISC-V targets:

PS C:\Users\luojia65> rustc --print target-list | findstr riscv
riscv32gc-unknown-linux-gnu
riscv32i-unknown-none-elf
riscv32imac-unknown-none-elf
riscv32imc-unknown-none-elf
riscv64gc-unknown-linux-gnu
riscv64gc-unknown-none-elf
riscv64imac-unknown-none-elf

As is listed, it's not listed by RISC-V's base extensions. RISC-V defined three base extensions: RV32I, RV32E and RV64I, and defined extension modules like M, A or C etc. addition to it. Here, current Rust gave us only limited combinations.

As RISC-V grows there could be more modules come out. We cannot make every combination for every modules (that's O(2^N) of work!). What make issues more is that there are operating system targets. For every operating system we are required to implement Rust toolchain in all combinations. That's a lot of targets which make code complex.

So we may keep:

riscv32i-unknown-linux-gnu
riscv32i-unknown-none-elf
riscv64i-unknown-linux-gnu
riscv64i-unknown-none-elf

... this means <base isa>-<vendor>-<platform> for target definition which can simplify software implementations in Rust and its ecosystem.

For example I have an operating system called HarmonyOS on RISC-V, we should implement only riscv64i-huawei-harmonyos and riscv32i-huawei-harmonyos etc., instead of somehow lots of target combinations.

When did these combinations of RISC-V Rust targets comes out and where was this idea come from? Can we make a modification to rustc to simplify modular ISA implementation like RISC-V on Rust?

1 Like

std/core is distributed precompiled per target, so while it's possible in some cases (I don't think you could build std without G) to use only I, this will result in a suboptimal std/core if you later include it in a build with additional extensions. Presumably the work from the std-aware Cargo working group may help fix this in the future.

4 Likes