Recently I camp up with an idea to implement RISC-V vector V into core::arch crate. I opened vadd.ll file to see how the target LLVM IR would look like, and I saw code like:
declare void @llvm.riscv.vse.mask.nxv1i64(
<vscale x 1 x i64>,
<vscale x 1 x i64>*,
<vscale x 1 x i1>,
i64);
define void @intrinsic_vse_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vse64.v v8, (a0), v0.t
; CHECK-NEXT: ret
entry:
call void @llvm.riscv.vse.mask.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i1> %2,
i64 %3)
ret void
}
This piece of code includes a vscale
and a special form to declare variable length vector like <vscale x 1 x i64>
.
Is there any possibility to generate such code using current rustc
compiler? Thanks!