Code duplication for atomic instructions

compiler
1

For the code

static some_var:AtomicI32 = AtomicI32::new(5);
#[no_mangle]
fn helper1() -> i32
{ some_var.fetch_or(10, Ordering::Release) }

The IR generated is,

; Function Attrs: inlinehint nounwind
define internal i32 @_ZN4core4sync6atomic9atomic_or17h709034a090513fd1E(ptr %dst, i32 %val, i8 %0) unnamed_addr #0 {
start:
%1 = alloca i32, align 4
%order = alloca i8, align 1
store i8 %0, ptr %order, align 1
%2 = load i8, ptr %order, align 1, !range !0, !noundef !1
%_4 = zext i8 %2 to i32
switch i32 %_4, label %bb2 [
i32 0, label %bb1
i32 1, label %bb7
i32 2, label %bb5
i32 3, label %bb9
i32 4, label %bb3
]

bb2: ; preds = %start
unreachable

bb1: ; preds = %start
%3 = atomicrmw or ptr %dst, i32 %val monotonic, align 4
store i32 %3, ptr %1, align 4
br label %bb12

bb7: ; preds = %start
%4 = atomicrmw or ptr %dst, i32 %val release, align 4
store i32 %4, ptr %1, align 4
br label %bb12

bb5: ; preds = %start
%5 = atomicrmw or ptr %dst, i32 %val acquire, align 4
store i32 %5, ptr %1, align 4
br label %bb12

bb9: ; preds = %start
%6 = atomicrmw or ptr %dst, i32 %val acq_rel, align 4
store i32 %6, ptr %1, align 4
br label %bb12

bb3: ; preds = %start
%7 = atomicrmw or ptr %dst, i32 %val seq_cst, align 4
store i32 %7, ptr %1, align 4
br label %bb12

Even though, ordering is specified, code is generated for all the ordering.

2

That's only in debug mode. The ordering is specified as an enum value passed at run-time, so generating code for all possible cases is expected, however if you turn on optimizations[1], the situation becomes a lot better.

@_ZN10playground8some_var17h1d9f58d765bb4b47E = internal global <{ [4 x i8] }> <{ [4 x i8] c"\05\00\00\00" }>, align 4

; Function Attrs: mustprogress nofree norecurse nounwind nonlazybind willreturn uwtable
define i32 @helper1() unnamed_addr #0 {
start:
  %0 = atomicrmw or ptr @_ZN10playground8some_var17h1d9f58d765bb4b47E, i32 10 release, align 4
  ret i32 %0
}

  1. see the choice of “RELEASE” mode in that playground; you can create the IR yourself by running the “LLVM IR” mode instead of the “BUILD” action ↩︎

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