# Why rustc's RISC-V targets attach combinations of ISA to instruction base sets?

**URL:** <https://internals.rust-lang.org/t/why-rustcs-risc-v-targets-attach-combinations-of-isa-to-instruction-base-sets/13748>\
**Category:** compiler\
**Created:** [January 4, 2021, 3:47pm UTC](https://internals.rust-lang.org/t/why-rustcs-risc-v-targets-attach-combinations-of-isa-to-instruction-base-sets/13748 "2021-01-04T15:47:36Z")\
**Posts on this page:** 3\
**Page:** 1

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**Author:** ![luojia](https://sea2.discourse-cdn.com/flex002/user_avatar/internals.rust-lang.org/luojia/32/4483_2.png) [@luojia](https://internals.rust-lang.org/u/luojia)\
**Post date:** [January 4, 2021, 3:47pm UTC](https://internals.rust-lang.org/t/why-rustcs-risc-v-targets-attach-combinations-of-isa-to-instruction-base-sets/13748/1 "2021-01-04T15:47:36Z")

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By now, Rust supports the following RISC-V targets:

```rust
PS C:\Users\luojia65> rustc --print target-list | findstr riscv
riscv32gc-unknown-linux-gnu
riscv32i-unknown-none-elf
riscv32imac-unknown-none-elf
riscv32imc-unknown-none-elf
riscv64gc-unknown-linux-gnu
riscv64gc-unknown-none-elf
riscv64imac-unknown-none-elf

```

As is listed, it's not listed by RISC-V's base extensions. RISC-V defined three base extensions: `RV32I`, `RV32E` and `RV64I`, and defined extension modules like `M`, `A` or `C` etc. addition to it. Here, current Rust gave us only limited combinations.

As RISC-V grows there could be more modules come out. We cannot make every combination for every modules (that's `O(2^N)` of work!). What make issues more is that there are operating system targets. For every operating system we are required to implement Rust toolchain in all combinations. That's a lot of targets which make code complex.

So we may keep:

```rust
riscv32i-unknown-linux-gnu
riscv32i-unknown-none-elf
riscv64i-unknown-linux-gnu
riscv64i-unknown-none-elf

```

... this means `<base isa>-<vendor>-<platform>` for target definition which can simplify software implementations in Rust and its ecosystem.

For example I have an operating system called HarmonyOS on RISC-V, we should implement only `riscv64i-huawei-harmonyos` and `riscv32i-huawei-harmonyos` etc., instead of somehow lots of target combinations.

When did these combinations of RISC-V Rust targets comes out and where was this idea come from? Can we make a modification to rustc to simplify modular ISA implementation like RISC-V on Rust?

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**Author:** ![jethrogb](https://avatars.discourse-cdn.com/v4/letter/j/43a26b/32.png) [@jethrogb](https://internals.rust-lang.org/u/jethrogb)\
**Post date:** [January 4, 2021, 5:00pm UTC](https://internals.rust-lang.org/t/why-rustcs-risc-v-targets-attach-combinations-of-isa-to-instruction-base-sets/13748/2 "2021-01-04T17:00:56Z")

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`std`/`core` is distributed precompiled per target, so while it's possible in some cases (I don't think you could build `std` without `G`) to use only `I`, this will result in a suboptimal `std`/`core` if you later include it in a build with additional extensions. Presumably the work from the [std-aware Cargo working group](https://github.com/rust-lang/wg-cargo-std-aware) may help fix this in the future.

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**Author:** ![system](https://sea2.discourse-cdn.com/flex002/user_avatar/internals.rust-lang.org/system/32/14092_2.png) [@system](https://internals.rust-lang.org/u/system)\
**Post date:** [April 4, 2021, 5:01pm UTC](https://internals.rust-lang.org/t/why-rustcs-risc-v-targets-attach-combinations-of-isa-to-instruction-base-sets/13748/3 "2021-04-04T17:01:04Z")

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