Volatile and sensitive memory

language design
98

I was referring to the (presumably) usually non-volatile writes for the actual data to be transferred. By naive understanding of this process is that it goes something like:

  • normal writes for the data (e.g., the network package to send)
  • fence
  • volatile write putting the address of the data into some MMIO register

As others said, this sounds insufficient. Specifically, the compiler is allowed to reorder the following two lines, if it can show that x and y do not alias:

// x: *mut i32, y: *mut i32
x.write(42);
y.write_volatile(13);
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