# Stabilizing Linker Relaxation for RISC-V

**URL:** <https://internals.rust-lang.org/t/stabilizing-linker-relaxation-for-risc-v/23311>\
**Category:** compiler\
**Created:** [August 2, 2025, 2:42pm UTC](https://internals.rust-lang.org/t/stabilizing-linker-relaxation-for-risc-v/23311 "2025-08-02T14:42:37Z")\
**Posts on this page:** 1\
**Page:** 1

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**Author:** ![reynoldsbd](https://sea2.discourse-cdn.com/flex002/user_avatar/internals.rust-lang.org/reynoldsbd/32/13469_2.png) [@reynoldsbd](https://internals.rust-lang.org/u/reynoldsbd)\
**Post date:** [August 2, 2025, 2:42pm UTC](https://internals.rust-lang.org/t/stabilizing-linker-relaxation-for-risc-v/23311/1 "2025-08-02T14:42:37Z")

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Hi all! Looking to start a conversation about what it would take to stabilize the RISC-V “relax” target feature which was [added a few years back](https://github.com/rust-lang/rust/pull/109860).

Linker relaxation is an important optimization for RISC-V ([according to SiFive](https://www.sifive.com/blog/all-aboard-part-3-linker-relaxation-in-riscv-toolchain), “it has greatly shaped the design of the RISC-V ISA.”). We’re using it for Tock OS to realize something on the order of a 10% space savings for RISC-V targets. But this triggers a noisy compiler warning due to the feature being unstable.

What does the path look like for this feature to become stable?

(And as an aside, is there or should there be some mechanism to opt out of warnings for compiler features?)