# Adding access to the carry flag bit

**URL:** <https://internals.rust-lang.org/t/adding-access-to-the-carry-flag-bit/12854>\
**Category:** language design\
**Created:** [August 7, 2020, 4:54pm UTC](https://internals.rust-lang.org/t/adding-access-to-the-carry-flag-bit/12854 "2020-08-07T16:54:03Z")\
**Posts on this page:** 1\
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**Author:** ![Tom-Phinney](https://sea2.discourse-cdn.com/flex002/user_avatar/internals.rust-lang.org/tom-phinney/32/3299_2.png) [@Tom-Phinney](https://internals.rust-lang.org/u/Tom-Phinney)\
**Post date:** [August 12, 2020, 2:26pm UTC](https://internals.rust-lang.org/t/adding-access-to-the-carry-flag-bit/12854/13 "2020-08-12T14:26:13Z")

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Instruction-level access to a "carry bit", so that the value can be used as an input to a subsequent instruction, was trivial to implement in the early days of computing when each instruction was completed **before** the next instruction was begun.

For a modern, out-of-order, superscalar processor implementation that cost/benefit is reversed; the cost in gates and/or instruction-cycle slowdown of the "carry-bit feature" far, far outweighs any possible benefit. That is why RISC-V, which is a state-of-the-art computer architecture whose expected implementations span the range from embedded processors of 10k gate complexity (e.g., RV32EC) to superscalar processors with 100x more gates, does not materialize an instruction-stream-synchronous carry bit.

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_[View the full topic](https://internals.rust-lang.org/t/adding-access-to-the-carry-flag-bit/12854)._